%0 Conference Paper %1 conf/iscas/MuS99a %A Mu, Fenghao %A Svensson, Christer %B ISCAS (2) %D 1999 %I IEEE %K dblp %P 541-544 %T High speed multistage CMOS clock buffers with pulse width control loop. %U http://dblp.uni-trier.de/db/conf/iscas/iscas1999-2.html#MuS99a %@ 0-7803-5471-0

@inproceedings{conf/iscas/MuS99a, added-at = {2016-05-20T00:00:00.000+0200}, author = {Mu, Fenghao and Svensson, Christer}, biburl = {https://www.bibsonomy.org/bibtex/200f4aa49ef975dc45cf628ac7bc24f22/dblp}, booktitle = {ISCAS (2)}, crossref = {conf/iscas/1999}, ee = {http://dx.doi.org/10.1109/ISCAS.1999.780805}, interhash = {0c622f2475ab7a7bca4d48b7bc127701}, intrahash = {00f4aa49ef975dc45cf628ac7bc24f22}, isbn = {0-7803-5471-0}, keywords = {dblp}, pages = {541-544}, publisher = {IEEE}, timestamp = {2016-05-21T11:38:50.000+0200}, title = {High speed multistage CMOS clock buffers with pulse width control loop.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas1999-2.html#MuS99a}, year = 1999 }