%0 Conference Paper %1 conf/dac/ShinshaKSKI86 %A Shinsha, T. %A Kubo, T. %A Sakataya, Y. %A Koshishita, J. %A Ishihara, Koichiro %B DAC %D 1986 %E Thomas, Don %I IEEE Computer Society Press %K dblp %P 391-397 %T Incremental logic synthesis through gate logic structure identification. %U http://dblp.uni-trier.de/db/conf/dac/dac1986.html#ShinshaKSKI86

@inproceedings{conf/dac/ShinshaKSKI86, added-at = {2018-11-06T00:00:00.000+0100}, author = {Shinsha, T. and Kubo, T. and Sakataya, Y. and Koshishita, J. and Ishihara, Koichiro}, biburl = {https://www.bibsonomy.org/bibtex/242cbe8be6529ffa6bef34c85918a7cec/dblp}, booktitle = {DAC}, crossref = {conf/dac/1986}, editor = {Thomas, Don}, ee = {https://doi.org/10.1145/318013.318076}, interhash = {0c899298d95b6e291aff7ec6d672dd88}, intrahash = {42cbe8be6529ffa6bef34c85918a7cec}, keywords = {dblp}, pages = {391-397}, publisher = {IEEE Computer Society Press}, timestamp = {2018-11-07T16:13:50.000+0100}, title = {Incremental logic synthesis through gate logic structure identification.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac1986.html#ShinshaKSKI86}, year = 1986 }