Inproceedings,
7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.
J. Davis, P. Bunce, D. Henderson, Y. Chan, U. Srinivasan, D. Rodko, P. Patel, T. Knips, and T. Werner.ISSCC, page 324-325. IEEE, (2013)
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- conf/isscc/DavisBHCSRPKW13
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- inproceedings
- booktitle
- ISSCC
- year
- 2013
- pages
- 324-325
- publisher
- IEEE
- crossref
- conf/isscc/2013
- ee
- https://doi.org/10.1109/ISSCC.2013.6487754
- isbn
- 978-1-4673-4515-6
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2013.html#DavisBHCSRPKW13
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%1 conf/isscc/DavisBHCSRPKW13
%A Davis, John
%A Bunce, Paul
%A Henderson, Diana M.
%A Chan, Yuen H.
%A Srinivasan, Uma
%A Rodko, Daniel
%A Patel, Pradip
%A Knips, Thomas J.
%A Werner, Tobias
%B ISSCC
%D 2013
%I IEEE
%K dblp
%P 324-325
%T 7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2013.html#DavisBHCSRPKW13
%@ 978-1-4673-4515-6
@inproceedings{conf/isscc/DavisBHCSRPKW13,
added-at = {2023-09-19T00:00:00.000+0200},
author = {Davis, John and Bunce, Paul and Henderson, Diana M. and Chan, Yuen H. and Srinivasan, Uma and Rodko, Daniel and Patel, Pradip and Knips, Thomas J. and Werner, Tobias},
biburl = {https://www.bibsonomy.org/bibtex/2b8a3ee9e1440bf6c0e203f4276188a29/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2013},
ee = {https://doi.org/10.1109/ISSCC.2013.6487754},
interhash = {0fffaf80f8003fe441ed1293cd3ebbbd},
intrahash = {b8a3ee9e1440bf6c0e203f4276188a29},
isbn = {978-1-4673-4515-6},
keywords = {dblp},
pages = {324-325},
publisher = {IEEE},
timestamp = {2024-04-10T11:03:30.000+0200},
title = {7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2013.html#DavisBHCSRPKW13},
year = 2013
}