%0 Journal Article %1 journals/jssc/ZhangBCHMVWZB06 %A Zhang, Kevin %A Bhattacharya, Uddalak %A Chen, Zhanping %A Hamzaoglu, Fatih %A Murray, Daniel %A Vallepalli, Narendra %A Wang, Yih %A Zheng, Bo %A Bohr, Mark %D 2006 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 146-151 %T A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. %U http://dblp.uni-trier.de/db/journals/jssc/jssc41.html#ZhangBCHMVWZB06 %V 41

@article{journals/jssc/ZhangBCHMVWZB06, added-at = {2022-01-03T00:00:00.000+0100}, author = {Zhang, Kevin and Bhattacharya, Uddalak and Chen, Zhanping and Hamzaoglu, Fatih and Murray, Daniel and Vallepalli, Narendra and Wang, Yih and Zheng, Bo and Bohr, Mark}, biburl = {https://www.bibsonomy.org/bibtex/23814858d79d2b40a9c96b36a420bed3e/dblp}, ee = {https://doi.org/10.1109/JSSC.2005.859025}, interhash = {03544a6e051967a2e6e82593c41d0418}, intrahash = {3814858d79d2b40a9c96b36a420bed3e}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {146-151}, timestamp = {2024-04-08T10:43:55.000+0200}, title = {A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc41.html#ZhangBCHMVWZB06}, volume = 41, year = 2006 }