%0 Journal Article %1 journals/tvlsi/LinLC10 %A Lin, Ying-Zu %A Lin, Cheng-Wu %A Chang, Soon-Jyh %D 2010 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 3 %P 509-513 %T A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#LinLC10 %V 18

@article{journals/tvlsi/LinLC10, added-at = {2020-03-11T00:00:00.000+0100}, author = {Lin, Ying-Zu and Lin, Cheng-Wu and Chang, Soon-Jyh}, biburl = {https://www.bibsonomy.org/bibtex/29fce31045f9137e1af642e90846defad/dblp}, ee = {https://doi.org/10.1109/TVLSI.2009.2013628}, interhash = {04bbc19baedec1a60d4060e0d268da4f}, intrahash = {9fce31045f9137e1af642e90846defad}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 3, pages = {509-513}, timestamp = {2020-03-12T11:42:08.000+0100}, title = {A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi18.html#LinLC10}, volume = 18, year = 2010 }