%0 Conference Paper %1 conf/dac/AwanoS16 %A Awano, Hiromitsu %A Sato, Takashi %B DAC %D 2016 %I ACM %K dblp %P 115:1-115:6 %T Efficient transistor-level timing yield estimation via line sampling. %U http://dblp.uni-trier.de/db/conf/dac/dac2016.html#AwanoS16 %@ 978-1-4503-4236-0

@inproceedings{conf/dac/AwanoS16, added-at = {2022-10-02T00:00:00.000+0200}, author = {Awano, Hiromitsu and Sato, Takashi}, biburl = {https://www.bibsonomy.org/bibtex/252b9440038334cc8f18b1618e5d28d81/dblp}, booktitle = {DAC}, crossref = {conf/dac/2016}, ee = {https://doi.org/10.1145/2897937.2898016}, interhash = {0738d203c11e040f388d345003d47f57}, intrahash = {52b9440038334cc8f18b1618e5d28d81}, isbn = {978-1-4503-4236-0}, keywords = {dblp}, pages = {115:1-115:6}, publisher = {ACM}, timestamp = {2024-04-10T06:55:10.000+0200}, title = {Efficient transistor-level timing yield estimation via line sampling.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2016.html#AwanoS16}, year = 2016 }