%0 Conference Paper %1 conf/islped/KimCABS12 %A Kim, Daeyeon %A Chandra, Vikas %A Aitken, Robert C. %A Blaauw, David T. %A Sylvester, Dennis %B ISLPED %D 2012 %E Shanbhag, Naresh R. %E Poncino, Massimo %E Chou, Pai H. %E Amerasekera, Ajith %I ACM %K dblp %P 91-96 %T An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs. %U http://dblp.uni-trier.de/db/conf/islped/islped2012.html#KimCABS12 %@ 978-1-4503-1249-3

@inproceedings{conf/islped/KimCABS12, added-at = {2018-11-06T00:00:00.000+0100}, author = {Kim, Daeyeon and Chandra, Vikas and Aitken, Robert C. and Blaauw, David T. and Sylvester, Dennis}, biburl = {https://www.bibsonomy.org/bibtex/2e300e23770fcb1095daee9cb4d153c54/dblp}, booktitle = {ISLPED}, crossref = {conf/islped/2012}, editor = {Shanbhag, Naresh R. and Poncino, Massimo and Chou, Pai H. and Amerasekera, Ajith}, ee = {https://doi.org/10.1145/2333660.2333684}, interhash = {0ae0156dfe1e056ce1ccaa907d8ab839}, intrahash = {e300e23770fcb1095daee9cb4d153c54}, isbn = {978-1-4503-1249-3}, keywords = {dblp}, pages = {91-96}, publisher = {ACM}, timestamp = {2018-11-07T16:24:41.000+0100}, title = {An adaptive write word-line pulse width and voltage modulation architecture for bit-interleaved 8T SRAMs.}, url = {http://dblp.uni-trier.de/db/conf/islped/islped2012.html#KimCABS12}, year = 2012 }