%0 Conference Paper %1 conf/vlsid/IshiharaA02 %A Ishihara, Tohru %A Asada, Kunihiro %B ASP-DAC/VLSI Design %D 2002 %I IEEE Computer Society %K dblp %P 282-287 %T An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#IshiharaA02 %@ 0-7695-1299-2

@inproceedings{conf/vlsid/IshiharaA02, added-at = {2022-11-14T00:00:00.000+0100}, author = {Ishihara, Tohru and Asada, Kunihiro}, biburl = {https://www.bibsonomy.org/bibtex/2c676850bc97fb7eb133abc166e1ab687/dblp}, booktitle = {ASP-DAC/VLSI Design}, crossref = {conf/vlsid/2002}, ee = {https://dl.acm.org/doi/10.5555/832284.835513}, interhash = {0cb2d77f20d144a3cbb4b464831195a9}, intrahash = {c676850bc97fb7eb133abc166e1ab687}, isbn = {0-7695-1299-2}, keywords = {dblp}, pages = {282-287}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:13.000+0200}, title = {An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#IshiharaA02}, year = 2002 }