%0 Journal Article %1 journals/todaes/KaoL05 %A Kao, Chi-Chou %A Lai, Yen-Tai %D 2005 %J ACM Trans. Design Autom. Electr. Syst. %K dblp %N 1 %P 168-186 %T An efficient algorithm for finding the minimal-area FPGA technology mapping. %U http://dblp.uni-trier.de/db/journals/todaes/todaes10.html#KaoL05 %V 10

@article{journals/todaes/KaoL05, added-at = {2018-11-06T00:00:00.000+0100}, author = {Kao, Chi-Chou and Lai, Yen-Tai}, biburl = {https://www.bibsonomy.org/bibtex/21efce036cdac15f32b71bc848fb76dae/dblp}, ee = {https://doi.org/10.1145/1044111.1044121}, interhash = {0f7eb92c88e338665efc1ef9da53f50b}, intrahash = {1efce036cdac15f32b71bc848fb76dae}, journal = {ACM Trans. Design Autom. Electr. Syst.}, keywords = {dblp}, number = 1, pages = {168-186}, timestamp = {2018-11-07T12:23:44.000+0100}, title = {An efficient algorithm for finding the minimal-area FPGA technology mapping.}, url = {http://dblp.uni-trier.de/db/journals/todaes/todaes10.html#KaoL05}, volume = 10, year = 2005 }