%0 Conference Paper %1 conf/cts/SatoCMH16 %A Sato, Tomoaki %A Chivapreecha, Sorawat %A Moungnoul, Phichet %A Higuchi, Kohji %B CTS %D 2016 %E Smari, Waleed W. %E Natarian, Joseph %I IEEE Computer Society %K dblp %P 412-417 %T An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs. %U http://dblp.uni-trier.de/db/conf/cts/cts2016.html#SatoCMH16 %@ 978-1-5090-2300-4

@inproceedings{conf/cts/SatoCMH16, added-at = {2017-05-24T00:00:00.000+0200}, author = {Sato, Tomoaki and Chivapreecha, Sorawat and Moungnoul, Phichet and Higuchi, Kohji}, biburl = {https://www.bibsonomy.org/bibtex/2f28117ef3b7f990e4851395f83ca635b/dblp}, booktitle = {CTS}, crossref = {conf/cts/2016}, editor = {Smari, Waleed W. and Natarian, Joseph}, ee = {https://doi.org/10.1109/CTS.2016.0079}, interhash = {1245cae9582b50bfdad43d4dddb65640}, intrahash = {f28117ef3b7f990e4851395f83ca635b}, isbn = {978-1-5090-2300-4}, keywords = {dblp}, pages = {412-417}, publisher = {IEEE Computer Society}, timestamp = {2019-10-17T16:42:21.000+0200}, title = {An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs.}, url = {http://dblp.uni-trier.de/db/conf/cts/cts2016.html#SatoCMH16}, year = 2016 }