%0 Conference Paper %1 conf/cscwd/ZhuZCB10 %A Zhu, Limin %A Zhou, Qiang %A Cai, Yici %A Bian, Jinian %B CSCWD %D 2010 %E Shen, Weiming %E Gu, Ning %E Lu, Tun %E Barthès, Jean-Paul A. %E Luo, Junzhou %I IEEE %K dblp %P 701-706 %T An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. %U http://dblp.uni-trier.de/db/conf/cscwd/cscwd2010.html#ZhuZCB10 %@ 978-1-4244-6763-1

@inproceedings{conf/cscwd/ZhuZCB10, added-at = {2018-01-30T00:00:00.000+0100}, author = {Zhu, Limin and Zhou, Qiang and Cai, Yici and Bian, Jinian}, biburl = {https://www.bibsonomy.org/bibtex/2c636bc241111c526c128b51230489c99/dblp}, booktitle = {CSCWD}, crossref = {conf/cscwd/2010}, editor = {Shen, Weiming and Gu, Ning and Lu, Tun and Barthès, Jean-Paul A. and Luo, Junzhou}, ee = {https://doi.org/10.1109/CSCWD.2010.5471886}, interhash = {126408998e7e03b0afe773a9b071be0e}, intrahash = {c636bc241111c526c128b51230489c99}, isbn = {978-1-4244-6763-1}, keywords = {dblp}, pages = {701-706}, publisher = {IEEE}, timestamp = {2019-10-17T20:56:23.000+0200}, title = {An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.}, url = {http://dblp.uni-trier.de/db/conf/cscwd/cscwd2010.html#ZhuZCB10}, year = 2010 }