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%0 Conference Paper
%1 conf/fpl/VyasDTH16
%A Vyas, Shrikant
%A Dumpala, Naveen Kumar
%A Tessier, Russell
%A Holcomb, Daniel E.
%B FPL
%D 2016
%E Ienne, Paolo
%E Najjar, Walid A.
%E Anderson, Jason Helge
%E Brisk, Philip
%E Stechele, Walter
%I IEEE
%K
%P 1-4
%T Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.
%U http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#VyasDTH16
%@ 978-2-8399-1844-2
@inproceedings{conf/fpl/VyasDTH16,
added-at = {2023-12-12T18:32:40.000+0100},
author = {Vyas, Shrikant and Dumpala, Naveen Kumar and Tessier, Russell and Holcomb, Daniel E.},
biburl = {https://www.bibsonomy.org/bibtex/21ff6d01923e7175e45b01ed4f0d96dbb/admin},
booktitle = {FPL},
crossref = {conf/fpl/2016},
editor = {Ienne, Paolo and Najjar, Walid A. and Anderson, Jason Helge and Brisk, Philip and Stechele, Walter},
ee = {https://doi.org/10.1109/FPL.2016.7577307},
interhash = {13d2b81a410242ed2b2f64e43d8e2d22},
intrahash = {1ff6d01923e7175e45b01ed4f0d96dbb},
isbn = {978-2-8399-1844-2},
keywords = {},
pages = {1-4},
publisher = {IEEE},
timestamp = {2023-12-12T18:32:40.000+0100},
title = {Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement.},
url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2016.html#VyasDTH16},
year = 2016
}