%0 Journal Article %1 journals/jcsc/PraveenS18 %A Praveen, J. %A Swamy, M. N. Shanmukha %D 2018 %J J. Circuits Syst. Comput. %K dblp %N 5 %P 1850078:1-1850078:18 %T BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture. %U http://dblp.uni-trier.de/db/journals/jcsc/jcsc27.html#PraveenS18 %V 27

@article{journals/jcsc/PraveenS18, added-at = {2020-10-26T00:00:00.000+0100}, author = {Praveen, J. and Swamy, M. N. Shanmukha}, biburl = {https://www.bibsonomy.org/bibtex/231567517facc72388846912021ec050a/dblp}, ee = {https://doi.org/10.1142/S0218126618500780}, interhash = {15a102812cc27f34fe2ce0afc3101dd3}, intrahash = {31567517facc72388846912021ec050a}, journal = {J. Circuits Syst. Comput.}, keywords = {dblp}, number = 5, pages = {1850078:1-1850078:18}, timestamp = {2020-10-27T12:22:04.000+0100}, title = {BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture.}, url = {http://dblp.uni-trier.de/db/journals/jcsc/jcsc27.html#PraveenS18}, volume = 27, year = 2018 }