%0 Journal Article %1 journals/iet-cds/RoyMDSB19 %A Roy, Swarnil %A Mukherjee, Sagar %A Dutta, Arka %A Sarkar, Chandan Kumar %A Bose, Chayanika %D 2019 %J IET Circuits Devices Syst. %K dblp %N 3 %P 337-343 %T Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application. %U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds13.html#RoyMDSB19 %V 13

@article{journals/iet-cds/RoyMDSB19, added-at = {2022-10-02T00:00:00.000+0200}, author = {Roy, Swarnil and Mukherjee, Sagar and Dutta, Arka and Sarkar, Chandan Kumar and Bose, Chayanika}, biburl = {https://www.bibsonomy.org/bibtex/2b213cd43cf9e3147d4a5b61d04245f25/dblp}, ee = {https://doi.org/10.1049/iet-cds.2018.5199}, interhash = {170cb504489fa8e495c818abde628f76}, intrahash = {b213cd43cf9e3147d4a5b61d04245f25}, journal = {IET Circuits Devices Syst.}, keywords = {dblp}, number = 3, pages = {337-343}, timestamp = {2024-04-08T16:07:13.000+0200}, title = {Circuit performance analysis of graded doping of channel of DGMOS with high-k gate stack for analogue and digital application.}, url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds13.html#RoyMDSB19}, volume = 13, year = 2019 }