%0 Journal Article %1 journals/jssc/SzilagyiPHSTE19 %A Szilágyi, László %A Plíva, Jan %A Henker, Ronny %A Schoeniger, David %A Turkiewicz, Jaroslaw P. %A Ellinger, Frank %D 2019 %J IEEE J. Solid State Circuits %K dblp %N 3 %P 845-855 %T A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#SzilagyiPHSTE19 %V 54

@article{journals/jssc/SzilagyiPHSTE19, added-at = {2020-08-30T00:00:00.000+0200}, author = {Szilágyi, László and Plíva, Jan and Henker, Ronny and Schoeniger, David and Turkiewicz, Jaroslaw P. and Ellinger, Frank}, biburl = {https://www.bibsonomy.org/bibtex/21219aa3b20dfd8270c18fa4b38017cf2/dblp}, ee = {https://doi.org/10.1109/JSSC.2018.2885531}, interhash = {1c4cae9a7a21ee78736d2b91a07657e2}, intrahash = {1219aa3b20dfd8270c18fa4b38017cf2}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 3, pages = {845-855}, timestamp = {2020-08-31T11:43:59.000+0200}, title = {A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc54.html#SzilagyiPHSTE19}, volume = 54, year = 2019 }