%0 Journal Article %1 journals/mr/TsaiLYC08 %A Tsai, Tsung-Yueh %A Lai, Yi-Shao %A Yeh, Chang-Lin %A Chen, Rong-Sheng %D 2008 %J Microelectron. Reliab. %K dblp %N 5 %P 757-762 %T Structural design optimization for board-level drop reliability of wafer-level chip-scale packages. %U http://dblp.uni-trier.de/db/journals/mr/mr48.html#TsaiLYC08 %V 48

@article{journals/mr/TsaiLYC08, added-at = {2020-02-22T00:00:00.000+0100}, author = {Tsai, Tsung-Yueh and Lai, Yi-Shao and Yeh, Chang-Lin and Chen, Rong-Sheng}, biburl = {https://www.bibsonomy.org/bibtex/24140e879fea97c9edbf071386284ff2d/dblp}, ee = {https://doi.org/10.1016/j.microrel.2008.01.003}, interhash = {2190ecf4050a1fa32c3c57a138813d3e}, intrahash = {4140e879fea97c9edbf071386284ff2d}, journal = {Microelectron. Reliab.}, keywords = {dblp}, number = 5, pages = {757-762}, timestamp = {2020-02-25T13:28:39.000+0100}, title = {Structural design optimization for board-level drop reliability of wafer-level chip-scale packages.}, url = {http://dblp.uni-trier.de/db/journals/mr/mr48.html#TsaiLYC08}, volume = 48, year = 2008 }