%0 Conference Paper %1 conf/ismvl/KawahitoMIN92 %A Kawahito, Shoji %A Mitsui, Y. %A Ishida, Makoto %A Nakamura, Tetsuro %B ISMVL %D 1992 %I IEEE Computer Society %K dblp %P 337-345 %T Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl1992.html#KawahitoMIN92 %@ 0-8186-2680-1

@inproceedings{conf/ismvl/KawahitoMIN92, added-at = {2023-03-23T00:00:00.000+0100}, author = {Kawahito, Shoji and Mitsui, Y. and Ishida, Makoto and Nakamura, Tetsuro}, biburl = {https://www.bibsonomy.org/bibtex/2ecfb3a89946240c731d3059b9dcb9570/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/1992}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISMVL.1992.186815}, interhash = {1236952e0e237779141fe72928165cce}, intrahash = {ecfb3a89946240c731d3059b9dcb9570}, isbn = {0-8186-2680-1}, keywords = {dblp}, pages = {337-345}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T15:36:56.000+0200}, title = {Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl1992.html#KawahitoMIN92}, year = 1992 }