%0 Journal Article %1 journals/tcas/BellasiB17 %A Bellasi, David E. %A Benini, Luca %D 2017 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 9 %P 2322-2333 %T Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI64.html#BellasiB17 %V 64-I

@article{journals/tcas/BellasiB17, added-at = {2020-05-22T00:00:00.000+0200}, author = {Bellasi, David E. and Benini, Luca}, biburl = {https://www.bibsonomy.org/bibtex/20d85bbc5430414b23df96de55a1ab859/dblp}, ee = {https://doi.org/10.1109/TCSI.2017.2694322}, interhash = {236c854316bee1b6bab1ed51b4d36410}, intrahash = {0d85bbc5430414b23df96de55a1ab859}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 9, pages = {2322-2333}, timestamp = {2020-05-23T12:31:05.000+0200}, title = {Smart Energy-Efficient Clock Synthesizer for Duty-Cycled Sensor SoCs in 65 nm/28nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI64.html#BellasiB17}, volume = {64-I}, year = 2017 }