%0 Conference Paper %1 conf/ipps/SingapuraPP15 %A Singapura, Shreyas G. %A Panangadan, Anand V. %A Prasanna, Viktor K. %B IPDPS Workshops %D 2015 %I IEEE Computer Society %K dblp %P 154-162 %T Performance Modeling of Matrix Multiplication on 3D Memory Integrated FPGA. %U http://dblp.uni-trier.de/db/conf/ipps/ipdps2015w.html#SingapuraPP15 %@ 978-1-4673-7684-6

@inproceedings{conf/ipps/SingapuraPP15, added-at = {2023-03-24T00:00:00.000+0100}, author = {Singapura, Shreyas G. and Panangadan, Anand V. and Prasanna, Viktor K.}, biburl = {https://www.bibsonomy.org/bibtex/208579863b872c6ac5f377f06ea2fed1c/dblp}, booktitle = {IPDPS Workshops}, crossref = {conf/ipps/2015w}, ee = {https://doi.ieeecomputersociety.org/10.1109/IPDPSW.2015.133}, interhash = {2a3dc6a9bf22527ff91e9d9dff7af1a4}, intrahash = {08579863b872c6ac5f377f06ea2fed1c}, isbn = {978-1-4673-7684-6}, keywords = {dblp}, pages = {154-162}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T13:25:21.000+0200}, title = {Performance Modeling of Matrix Multiplication on 3D Memory Integrated FPGA.}, url = {http://dblp.uni-trier.de/db/conf/ipps/ipdps2015w.html#SingapuraPP15}, year = 2015 }