%0 Conference Paper %1 conf/newcas/KatoTS15 %A Kato, Kazunari %A Takahashi, Yasuhiro %A Sekine, Toshikazu %B NEWCAS %D 2015 %I IEEE %K dblp %P 1-4 %T A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. %U http://dblp.uni-trier.de/db/conf/newcas/newcas2015.html#KatoTS15 %@ 978-1-4799-8893-8

@inproceedings{conf/newcas/KatoTS15, added-at = {2018-11-02T00:00:00.000+0100}, author = {Kato, Kazunari and Takahashi, Yasuhiro and Sekine, Toshikazu}, biburl = {https://www.bibsonomy.org/bibtex/22abcf426affb37f8e683c5c6ae62fb58/dblp}, booktitle = {NEWCAS}, crossref = {conf/newcas/2015}, ee = {https://doi.org/10.1109/NEWCAS.2015.7182098}, interhash = {2ae78565b1a731274b528e46ab5c80ac}, intrahash = {2abcf426affb37f8e683c5c6ae62fb58}, isbn = {978-1-4799-8893-8}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2019-10-17T22:48:09.000+0200}, title = {A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic.}, url = {http://dblp.uni-trier.de/db/conf/newcas/newcas2015.html#KatoTS15}, year = 2015 }