%0 Conference Paper %1 conf/vlsid/GargCSK06 %A Garg, Vivek %A Chandrasekhar, Vikram %A Sashikánth, Milagros %A Kamakoti, V. %B VLSI Design %D 2006 %I IEEE Computer Society %K dblp %P 507-510 %T An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#GargCSK06 %@ 0-7695-2502-4

@inproceedings{conf/vlsid/GargCSK06, added-at = {2023-03-24T00:00:00.000+0100}, author = {Garg, Vivek and Chandrasekhar, Vikram and Sashikánth, Milagros and Kamakoti, V.}, biburl = {https://www.bibsonomy.org/bibtex/2ea1283488ba241ef41ead4073d1d5d39/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2006}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2006.38}, interhash = {2dadeaef92e5eaf03ff5d08ffa1fce1f}, intrahash = {ea1283488ba241ef41ead4073d1d5d39}, isbn = {0-7695-2502-4}, keywords = {dblp}, pages = {507-510}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:52.000+0200}, title = {An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2006.html#GargCSK06}, year = 2006 }