%0 Conference Paper %1 conf/vlsi/JaiswalS15 %A Jaiswal, Manish Kumar %A So, Hayden Kwok-Hay %B VLSI-SoC %D 2015 %I IEEE %K dblp %P 213-218 %T Dual-mode double precision / two-parallel single precision floating point multiplier architecture. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#JaiswalS15 %@ 978-1-4673-9140-5

@inproceedings{conf/vlsi/JaiswalS15, added-at = {2019-09-16T00:00:00.000+0200}, author = {Jaiswal, Manish Kumar and So, Hayden Kwok-Hay}, biburl = {https://www.bibsonomy.org/bibtex/2d48958f0ef734fc92ddae8a14422e831/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2015soc}, ee = {https://www.wikidata.org/entity/Q59789517}, interhash = {2e7086e4681fd29d5aa723dba71b4401}, intrahash = {d48958f0ef734fc92ddae8a14422e831}, isbn = {978-1-4673-9140-5}, keywords = {dblp}, pages = {213-218}, publisher = {IEEE}, timestamp = {2019-10-17T14:01:58.000+0200}, title = {Dual-mode double precision / two-parallel single precision floating point multiplier architecture.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2015.html#JaiswalS15}, year = 2015 }