%0 Journal Article %1 journals/jssc/ChengSC08 %A Cheng, Kuo-Hsing %A Su, Chia-Wei %A Chang, Kai-Fei %D 2008 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 399-413 %T A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation. %U http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#ChengSC08 %V 43

@article{journals/jssc/ChengSC08, added-at = {2020-08-30T00:00:00.000+0200}, author = {Cheng, Kuo-Hsing and Su, Chia-Wei and Chang, Kai-Fei}, biburl = {https://www.bibsonomy.org/bibtex/280af2e04d4b27352365a4d98eb713205/dblp}, ee = {https://doi.org/10.1109/JSSC.2007.914286}, interhash = {392b9a03c0e418a353183968a6e47fa9}, intrahash = {80af2e04d4b27352365a4d98eb713205}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 2, pages = {399-413}, timestamp = {2020-08-31T11:44:06.000+0200}, title = {A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#ChengSC08}, volume = 43, year = 2008 }