%0 Journal Article %1 journals/tvlsi/ParkZEO16 %A Park, Jaeyoung %A Zheng, Tianhao %A Erez, Mattan %A Orshansky, Michael %D 2016 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 4 %P 1351-1360 %T Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#ParkZEO16 %V 24

@article{journals/tvlsi/ParkZEO16, added-at = {2024-02-05T00:00:00.000+0100}, author = {Park, Jaeyoung and Zheng, Tianhao and Erez, Mattan and Orshansky, Michael}, biburl = {https://www.bibsonomy.org/bibtex/23ebb68002f7af9f440941bf0458ae3b0/dblp}, ee = {https://doi.org/10.1109/TVLSI.2015.2449739}, interhash = {396c82fd7bdb0239729d52d5eb13ee94}, intrahash = {3ebb68002f7af9f440941bf0458ae3b0}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 4, pages = {1351-1360}, timestamp = {2024-04-08T14:31:56.000+0200}, title = {Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi24.html#ParkZEO16}, volume = 24, year = 2016 }