%0 Journal Article %1 journals/tcad/ZhaoXWWWZTFL23 %A Zhao, Wei %A Xu, Jie %A Wei, Xueliang %A Wu, Bing %A Wang, Chengning %A Zhu, Weilin %A Tong, Wei %A Feng, Dan %A Liu, Jingning %D 2023 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 1 %P 122-135 %T A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System. %U http://dblp.uni-trier.de/db/journals/tcad/tcad42.html#ZhaoXWWWZTFL23 %V 42

@article{journals/tcad/ZhaoXWWWZTFL23, added-at = {2023-01-19T00:00:00.000+0100}, author = {Zhao, Wei and Xu, Jie and Wei, Xueliang and Wu, Bing and Wang, Chengning and Zhu, Weilin and Tong, Wei and Feng, Dan and Liu, Jingning}, biburl = {https://www.bibsonomy.org/bibtex/25261de7949a2518317931e651b6caed4/dblp}, ee = {https://doi.org/10.1109/TCAD.2022.3169458}, interhash = {3b0342f62cb2536c839f026dc756a234}, intrahash = {5261de7949a2518317931e651b6caed4}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 1, pages = {122-135}, timestamp = {2024-04-08T19:46:40.000+0200}, title = {A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad42.html#ZhaoXWWWZTFL23}, volume = 42, year = 2023 }