%0 Conference Paper %1 7529865 %A Nolting, S. %A Payá-Vayá, G. %A Giesemann, F. %A Blume, H. %A Niemann, S. %A Müeller-Schloer, C. %B 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) %D 2016 %K myown %P 172-180 %R 10.1109/IPDPSW.2016.158 %T Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture %U http://ieeexplore.ieee.org/document/7529865/ %X The rising demands for computational performance is a current trend in our increasingly digital world. Keeping up with this trend poses a challenge for every embedded processor system. This paper proposes the use of reconfigurable processor architectures to increase ön demand" processing performance while running a specific target application. The reconfiguration is used to interchange specialized co-processors attached to a static soft-core processor during run-time. Different self-optimization software-hardware substitution mechanisms, inspired by the field of organic computing, are implemented and evaluated using two different synthetic benchmarks and an exemplary application from the field of parallel robotics. For a reduced number of reconfigurable co-processors, the results show, that the proposed software-hardware reconfiguration strategy provides, in general, better trade-offs between the required hardware resources and performance improvement when compared to the equivalent soft-core processor with the same number of static co-processors.

@inproceedings{7529865, abstract = {The rising demands for computational performance is a current trend in our increasingly digital world. Keeping up with this trend poses a challenge for every embedded processor system. This paper proposes the use of reconfigurable processor architectures to increase "on demand" processing performance while running a specific target application. The reconfiguration is used to interchange specialized co-processors attached to a static soft-core processor during run-time. Different self-optimization software-hardware substitution mechanisms, inspired by the field of organic computing, are implemented and evaluated using two different synthetic benchmarks and an exemplary application from the field of parallel robotics. For a reduced number of reconfigurable co-processors, the results show, that the proposed software-hardware reconfiguration strategy provides, in general, better trade-offs between the required hardware resources and performance improvement when compared to the equivalent soft-core processor with the same number of static co-processors.}, added-at = {2017-07-04T20:54:54.000+0200}, author = {Nolting, S. and Payá-Vayá, G. and Giesemann, F. and Blume, H. and Niemann, S. and Müeller-Schloer, C.}, biburl = {https://www.bibsonomy.org/bibtex/22ca5cfa910403a41e233543c9f70f80e/guipava}, booktitle = {2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, description = {Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture - IEEE Xplore Document}, doi = {10.1109/IPDPSW.2016.158}, interhash = {429f7bfb9a5d79bdd1f16879fd9e584f}, intrahash = {2ca5cfa910403a41e233543c9f70f80e}, keywords = {myown}, month = may, pages = {172-180}, timestamp = {2017-07-27T14:29:33.000+0200}, title = {Dynamic Self-Reconfiguration of a MIPS-Based Soft-Processor Architecture}, url = {http://ieeexplore.ieee.org/document/7529865/}, year = 2016 }