Inproceedings,
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics.
S. Barve, S. Raveendran, C. Korde, T. Panigrahi, N. Kumar, and M. Vasantha.iSES, page 6-10. IEEE, (2018)
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- BibTeX key
- conf/ises/BarveRKPKV18
- entry type
- inproceedings
- booktitle
- iSES
- year
- 2018
- pages
- 6-10
- publisher
- IEEE
- crossref
- conf/ises/2018
- ee
- https://doi.org/10.1109/iSES.2018.00012
- isbn
- 978-1-5386-9172-4
- url
- http://dblp.uni-trier.de/db/conf/ises/ises2018.html#BarveRKPKV18
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- please select -%0 Conference Paper
%1 conf/ises/BarveRKPKV18
%A Barve, Sampada
%A Raveendran, Sithara
%A Korde, Charudatta
%A Panigrahi, Trilochan
%A Kumar, Nithin Y. B.
%A Vasantha, M. H.
%B iSES
%D 2018
%I IEEE
%K dblp
%P 6-10
%T FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics.
%U http://dblp.uni-trier.de/db/conf/ises/ises2018.html#BarveRKPKV18
%@ 978-1-5386-9172-4
@inproceedings{conf/ises/BarveRKPKV18,
added-at = {2022-01-03T00:00:00.000+0100},
author = {Barve, Sampada and Raveendran, Sithara and Korde, Charudatta and Panigrahi, Trilochan and Kumar, Nithin Y. B. and Vasantha, M. H.},
biburl = {https://www.bibsonomy.org/bibtex/2bc1ac8de4ee48f5072fc095541afd564/dblp},
booktitle = {iSES},
crossref = {conf/ises/2018},
ee = {https://doi.org/10.1109/iSES.2018.00012},
interhash = {454088efcb60b4e0851aeafac353e7e8},
intrahash = {bc1ac8de4ee48f5072fc095541afd564},
isbn = {978-1-5386-9172-4},
keywords = {dblp},
pages = {6-10},
publisher = {IEEE},
timestamp = {2024-04-09T23:26:47.000+0200},
title = {FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics.},
url = {http://dblp.uni-trier.de/db/conf/ises/ises2018.html#BarveRKPKV18},
year = 2018
}