%0 Journal Article %1 journals/dt/PancholyRM92 %A Pancholy, Ashish %A Rajski, Janusz %A McNaughton, Larry J. %D 1992 %J IEEE Des. Test Comput. %K dblp %N 1 %P 72-83 %T Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. %U http://dblp.uni-trier.de/db/journals/dt/dt9.html#PancholyRM92 %V 9

@article{journals/dt/PancholyRM92, added-at = {2020-05-17T00:00:00.000+0200}, author = {Pancholy, Ashish and Rajski, Janusz and McNaughton, Larry J.}, biburl = {https://www.bibsonomy.org/bibtex/2f841ae2871f92aa7de2668a5cd6ae888/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/54.124519}, interhash = {45b706a05983b0de631a00234122c131}, intrahash = {f841ae2871f92aa7de2668a5cd6ae888}, journal = {IEEE Des. Test Comput.}, keywords = {dblp}, number = 1, pages = {72-83}, timestamp = {2020-05-19T12:21:31.000+0200}, title = {Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits.}, url = {http://dblp.uni-trier.de/db/journals/dt/dt9.html#PancholyRM92}, volume = 9, year = 1992 }