%0 Journal Article %1 journals/tcas/HuangZL15 %A Huang, Kejie %A Zhao, Rong %A Lian, Yong %D 2015 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 4 %P 1109-1116 %T A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory. %U http://dblp.uni-trier.de/db/journals/tcas/tcasI62.html#HuangZL15 %V 62-I

@article{journals/tcas/HuangZL15, added-at = {2022-04-21T00:00:00.000+0200}, author = {Huang, Kejie and Zhao, Rong and Lian, Yong}, biburl = {https://www.bibsonomy.org/bibtex/2d368386f2ec9c48515dfc7c81fa36418/dblp}, ee = {https://doi.org/10.1109/TCSI.2015.2388833}, interhash = {47cfa5a01f764bf3ed1e1194fa786b56}, intrahash = {d368386f2ec9c48515dfc7c81fa36418}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 4, pages = {1109-1116}, timestamp = {2024-04-09T06:14:01.000+0200}, title = {A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasI62.html#HuangZL15}, volume = {62-I}, year = 2015 }