%0 Conference Paper %1 conf/ats/BonhommeGGLP01 %A Bonhomme, Yannick %A Girard, Patrick %A Guiller, Loïs %A Landrault, Christian %A Pravossoudovitch, Serge %B Asian Test Symposium %D 2001 %I IEEE Computer Society %K dblp %P 253-258 %T A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. %U http://dblp.uni-trier.de/db/conf/ats/ats2001.html#BonhommeGGLP01 %@ 0-7695-1378-6

@inproceedings{conf/ats/BonhommeGGLP01, added-at = {2023-03-24T00:00:00.000+0100}, author = {Bonhomme, Yannick and Girard, Patrick and Guiller, Loïs and Landrault, Christian and Pravossoudovitch, Serge}, biburl = {https://www.bibsonomy.org/bibtex/2d9c60c31f3d8623009a3c011c62ea4b2/dblp}, booktitle = {Asian Test Symposium}, crossref = {conf/ats/2001}, ee = {https://doi.ieeecomputersociety.org/10.1109/ATS.2001.990291}, interhash = {4aa1a3da76c67e9ef3c8073959288116}, intrahash = {d9c60c31f3d8623009a3c011c62ea4b2}, isbn = {0-7695-1378-6}, keywords = {dblp}, pages = {253-258}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T06:35:48.000+0200}, title = {A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.}, url = {http://dblp.uni-trier.de/db/conf/ats/ats2001.html#BonhommeGGLP01}, year = 2001 }