%0 Conference Paper %1 conf/cav/VijayaraghavanC15 %A Vijayaraghavan, Muralidaran %A Chlipala, Adam %A Arvind, %A Dave, Nirav %B CAV (2) %D 2015 %E Kroening, Daniel %E Pasareanu, Corina S. %I Springer %K dblp %P 109-127 %T Modular Deductive Verification of Multiprocessor Hardware Designs. %U http://dblp.uni-trier.de/db/conf/cav/cav2015.html#VijayaraghavanC15 %V 9207 %@ 978-3-319-21667-6

@inproceedings{conf/cav/VijayaraghavanC15, added-at = {2019-08-20T00:00:00.000+0200}, author = {Vijayaraghavan, Muralidaran and Chlipala, Adam and Arvind and Dave, Nirav}, biburl = {https://www.bibsonomy.org/bibtex/278f07ead70219c025e3ba6749382f86d/dblp}, booktitle = {CAV (2)}, crossref = {conf/cav/2015}, editor = {Kroening, Daniel and Pasareanu, Corina S.}, ee = {https://doi.org/10.1007/978-3-319-21668-3_7}, interhash = {4afa3621ec7f49d4c4371044a3bf3c92}, intrahash = {78f07ead70219c025e3ba6749382f86d}, isbn = {978-3-319-21667-6}, keywords = {dblp}, pages = {109-127}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2019-08-21T12:23:18.000+0200}, title = {Modular Deductive Verification of Multiprocessor Hardware Designs.}, url = {http://dblp.uni-trier.de/db/conf/cav/cav2015.html#VijayaraghavanC15}, volume = 9207, year = 2015 }