%0 Conference Paper %1 conf/glvlsi/MangalagiriSYNXIK08 %A Mangalagiri, Prasanth %A Sarpatwari, Karthik %A Yanamandra, Aditya %A Narayanan, Vijaykrishnan %A Xie, Yuan %A Irwin, Mary Jane %A Karim, Osama Awadel %B ACM Great Lakes Symposium on VLSI %D 2008 %E Narayanan, Vijaykrishnan %E Yan, Zhiyuan %E Macii, Enrico %E Bhanja, Sanjukta %I ACM %K dblp %P 395-398 %T A low-power phase change memory based hybrid cache architecture. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#MangalagiriSYNXIK08 %@ 978-1-59593-999-9

@inproceedings{conf/glvlsi/MangalagiriSYNXIK08, added-at = {2018-11-06T00:00:00.000+0100}, author = {Mangalagiri, Prasanth and Sarpatwari, Karthik and Yanamandra, Aditya and Narayanan, Vijaykrishnan and Xie, Yuan and Irwin, Mary Jane and Karim, Osama Awadel}, biburl = {https://www.bibsonomy.org/bibtex/2288b0e1a0edac3ce5527669858b74c65/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2008}, editor = {Narayanan, Vijaykrishnan and Yan, Zhiyuan and Macii, Enrico and Bhanja, Sanjukta}, ee = {https://doi.org/10.1145/1366110.1366204}, interhash = {4b307d16ad16fd6856680a96d1a31bda}, intrahash = {288b0e1a0edac3ce5527669858b74c65}, isbn = {978-1-59593-999-9}, keywords = {dblp}, pages = {395-398}, publisher = {ACM}, timestamp = {2018-11-07T14:25:13.000+0100}, title = {A low-power phase change memory based hybrid cache architecture.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2008.html#MangalagiriSYNXIK08}, year = 2008 }