%0 Conference Paper %1 conf/aspdac/MatsunagaKM10 %A Matsunaga, Taeko %A Kimura, Shinji %A Matsunaga, Yusuke %B ASP-DAC %D 2010 %I IEEE %K dblp %P 337-342 %T Multi-operand adder synthesis on FPGAs using generalized parallel counters. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#MatsunagaKM10 %@ 978-1-60558-837-7

@inproceedings{conf/aspdac/MatsunagaKM10, added-at = {2017-05-26T00:00:00.000+0200}, author = {Matsunaga, Taeko and Kimura, Shinji and Matsunaga, Yusuke}, biburl = {https://www.bibsonomy.org/bibtex/2d30386f66ddf65b853702e33fcf613ec/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2010}, ee = {http://dl.acm.org/citation.cfm?id=1899793}, interhash = {4c341aa893d666ad2f694ab84fbf7238}, intrahash = {d30386f66ddf65b853702e33fcf613ec}, isbn = {978-1-60558-837-7}, keywords = {dblp}, pages = {337-342}, publisher = {IEEE}, timestamp = {2019-10-17T16:46:10.000+0200}, title = {Multi-operand adder synthesis on FPGAs using generalized parallel counters.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2010.html#MatsunagaKM10}, year = 2010 }