%0 Journal Article %1 journals/tcad/FlachRPJR14 %A Flach, Guilherme %A Reimann, Tiago %A Posser, Gracieli %A Johann, Marcelo O. %A Reis, Ricardo %D 2014 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 4 %P 546-557 %T Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. %U http://dblp.uni-trier.de/db/journals/tcad/tcad33.html#FlachRPJR14 %V 33

@article{journals/tcad/FlachRPJR14, added-at = {2020-09-24T00:00:00.000+0200}, author = {Flach, Guilherme and Reimann, Tiago and Posser, Gracieli and Johann, Marcelo O. and Reis, Ricardo}, biburl = {https://www.bibsonomy.org/bibtex/2d2eeccd336311f2d469a3c0ce089b494/dblp}, ee = {https://doi.org/10.1109/TCAD.2014.2305847}, interhash = {4c7cade49992b2df4afa5af4c3fd9820}, intrahash = {d2eeccd336311f2d469a3c0ce089b494}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 4, pages = {546-557}, timestamp = {2020-09-25T11:50:01.000+0200}, title = {Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad33.html#FlachRPJR14}, volume = 33, year = 2014 }