%0 Journal Article %1 journals/tcad/LiLCP08 %A Li, Xin %A Le, Jiayong %A Celik, Mustafa %A Pileggi, Lawrence T. %D 2008 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 6 %P 1041-1054 %T Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. %U http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#LiLCP08 %V 27

@article{journals/tcad/LiLCP08, added-at = {2020-09-24T00:00:00.000+0200}, author = {Li, Xin and Le, Jiayong and Celik, Mustafa and Pileggi, Lawrence T.}, biburl = {https://www.bibsonomy.org/bibtex/299ee2cf4cb67206b6e52e2743d568eee/dblp}, ee = {https://doi.org/10.1109/TCAD.2008.923241}, interhash = {4cf9cf7c79b623dc428da287e15d086c}, intrahash = {99ee2cf4cb67206b6e52e2743d568eee}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 6, pages = {1041-1054}, timestamp = {2020-09-25T11:48:35.000+0200}, title = {Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#LiLCP08}, volume = 27, year = 2008 }