%0 Journal Article %1 journals/jucs/PerezBTW07 %A Pérez, Oscar %A Berviller, Yves %A Tanougast, Camel %A Weber, Serge %D 2007 %J J. Univers. Comput. Sci. %K dblp %N 3 %P 349-362 %T The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation. %U http://dblp.uni-trier.de/db/journals/jucs/jucs13.html#PerezBTW07 %V 13

@article{journals/jucs/PerezBTW07, added-at = {2023-09-07T00:00:00.000+0200}, author = {Pérez, Oscar and Berviller, Yves and Tanougast, Camel and Weber, Serge}, biburl = {https://www.bibsonomy.org/bibtex/27278ee15ebe1c8907a39e5dc39eb8c79/dblp}, ee = {https://doi.org/10.3217/jucs-013-03-0349}, interhash = {504ba4abc0d1f77a4f75280d4e3ed525}, intrahash = {7278ee15ebe1c8907a39e5dc39eb8c79}, journal = {J. Univers. Comput. Sci.}, keywords = {dblp}, number = 3, pages = {349-362}, timestamp = {2024-04-08T15:57:55.000+0200}, title = {The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation.}, url = {http://dblp.uni-trier.de/db/journals/jucs/jucs13.html#PerezBTW07}, volume = 13, year = 2007 }