%0 Conference Paper %1 conf/ats/ChiangHCPL15 %A Chiang, Kuan-Ying %A Ho, Yu-Hao %A Chen, Yo-Wei %A Pan, Cheng-Sheng %A Li, James Chien-Mo %B ATS %D 2015 %I IEEE Computer Society %K dblp %P 181-186 %T Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. %U http://dblp.uni-trier.de/db/conf/ats/ats2015.html#ChiangHCPL15 %@ 978-1-4673-9739-1

@inproceedings{conf/ats/ChiangHCPL15, added-at = {2023-03-24T00:00:00.000+0100}, author = {Chiang, Kuan-Ying and Ho, Yu-Hao and Chen, Yo-Wei and Pan, Cheng-Sheng and Li, James Chien-Mo}, biburl = {https://www.bibsonomy.org/bibtex/23506f50aa7624fd5d613ae186376d537/dblp}, booktitle = {ATS}, crossref = {conf/ats/2015}, ee = {https://doi.ieeecomputersociety.org/10.1109/ATS.2015.38}, interhash = {512d586ea6c2f1827a0212258a923ad2}, intrahash = {3506f50aa7624fd5d613ae186376d537}, isbn = {978-1-4673-9739-1}, keywords = {dblp}, pages = {181-186}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T06:36:42.000+0200}, title = {Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.}, url = {http://dblp.uni-trier.de/db/conf/ats/ats2015.html#ChiangHCPL15}, year = 2015 }