%0 Journal Article %1 journals/ieicet/MoshnyagaMT95 %A Moshnyaga, Vasily G. %A Mori, Yutaka %A Tamaru, Keikichi %D 1995 %J IEICE Trans. Inf. Syst. %K dblp %N 3 %P 252-255 %T Register-Transfer Module Selection for Sub-Micron ASIC Design. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet78d.html#MoshnyagaMT95 %V 78-D

@article{journals/ieicet/MoshnyagaMT95, added-at = {2020-04-11T00:00:00.000+0200}, author = {Moshnyaga, Vasily G. and Mori, Yutaka and Tamaru, Keikichi}, biburl = {https://www.bibsonomy.org/bibtex/2a7184fe9ac711cd053a4f79479e1533f/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e78-d_3_252}, interhash = {51c2fe4f60a8be943ddae8fab826824f}, intrahash = {a7184fe9ac711cd053a4f79479e1533f}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 3, pages = {252-255}, timestamp = {2020-04-14T11:44:21.000+0200}, title = {Register-Transfer Module Selection for Sub-Micron ASIC Design.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet78d.html#MoshnyagaMT95}, volume = {78-D}, year = 1995 }