%0 Conference Paper %1 conf/icecsys/WuW04 %A Wu, Chung-Yu %A Wang, Jen-Chieh %B ICECS %D 2004 %I IEEE %K dblp %P 191-194 %T Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design. %U http://dblp.uni-trier.de/db/conf/icecsys/icecsys2004.html#WuW04 %@ 0-7803-8715-5

@inproceedings{conf/icecsys/WuW04, added-at = {2017-05-23T00:00:00.000+0200}, author = {Wu, Chung-Yu and Wang, Jen-Chieh}, biburl = {https://www.bibsonomy.org/bibtex/2f7b63bfc5e9b60e9ab723f9922aa1284/dblp}, booktitle = {ICECS}, crossref = {conf/icecsys/2004}, ee = {https://doi.org/10.1109/ICECS.2004.1399647}, interhash = {51ee33fff4ee4678a78435cd3af263c3}, intrahash = {f7b63bfc5e9b60e9ab723f9922aa1284}, isbn = {0-7803-8715-5}, keywords = {dblp}, pages = {191-194}, publisher = {IEEE}, timestamp = {2019-10-17T19:50:21.000+0200}, title = {Optimal structure of interconnection lines for GHz giga-scale nano-CMOS system-on-chip design.}, url = {http://dblp.uni-trier.de/db/conf/icecsys/icecsys2004.html#WuW04}, year = 2004 }