%0 Journal Article %1 journals/tse/ParnasC86a %A Parnas, David Lorge %A Clements, Paul C. %D 1986 %J IEEE Trans. Software Eng. %K dblp %N 8 %P 874 %T Correction to Ä Rational Design Process: How and Why to Fake It". %U http://dblp.uni-trier.de/db/journals/tse/tse12.html#ParnasC86a %V 12

@article{journals/tse/ParnasC86a, added-at = {2015-12-10T00:00:00.000+0100}, author = {Parnas, David Lorge and Clements, Paul C.}, biburl = {https://www.bibsonomy.org/bibtex/20d1f82d5f48c9f3ab338c521414ed386/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TSE.1986.6312991}, interhash = {52c30a8ed741c426c24a56fcf2369910}, intrahash = {0d1f82d5f48c9f3ab338c521414ed386}, journal = {IEEE Trans. Software Eng.}, keywords = {dblp}, note = {see: IEEE Trans. Software Eng. 12(2): 251-257 (1986)}, number = 8, pages = 874, timestamp = {2015-12-12T11:52:47.000+0100}, title = {Correction to "A Rational Design Process: How and Why to Fake It".}, url = {http://dblp.uni-trier.de/db/journals/tse/tse12.html#ParnasC86a}, volume = 12, year = 1986 }