%0 Journal Article %1 journals/jssc/SharmaCAHCD11 %A Sharma, Vibhu %A Cosemans, Stefan %A Ashouei, Maryam %A Huisken, Jos %A Catthoor, Francky %A Dehaene, Wim %D 2011 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2416-2430 %T A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy. %U http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#SharmaCAHCD11 %V 46

@article{journals/jssc/SharmaCAHCD11, added-at = {2022-06-23T00:00:00.000+0200}, author = {Sharma, Vibhu and Cosemans, Stefan and Ashouei, Maryam and Huisken, Jos and Catthoor, Francky and Dehaene, Wim}, biburl = {https://www.bibsonomy.org/bibtex/2ac9cf1b904d317069159b0bf13f3b239/dblp}, ee = {https://doi.org/10.1109/JSSC.2011.2159056}, interhash = {153d3b3c99277d8c53e138a1c0c2f113}, intrahash = {ac9cf1b904d317069159b0bf13f3b239}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2416-2430}, timestamp = {2024-04-08T10:43:29.000+0200}, title = {A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc46.html#SharmaCAHCD11}, volume = 46, year = 2011 }