%0 Journal Article %1 journals/jsa/AgarwallaDS22 %A Agarwalla, Bindu %A Das, Shirshendu %A Sahu, Nilkanta %D 2022 %J J. Syst. Archit. %K dblp %P 102364 %T Process variation aware DRAM-Cache resizing. %U http://dblp.uni-trier.de/db/journals/jsa/jsa123.html#AgarwallaDS22 %V 123

@article{journals/jsa/AgarwallaDS22, added-at = {2022-02-23T00:00:00.000+0100}, author = {Agarwalla, Bindu and Das, Shirshendu and Sahu, Nilkanta}, biburl = {https://www.bibsonomy.org/bibtex/20a4a6ebd4bdf207b94b4eeb7cc170193/dblp}, ee = {https://doi.org/10.1016/j.sysarc.2021.102364}, interhash = {53fa25bbea8bf1db5e9a969c8047e327}, intrahash = {0a4a6ebd4bdf207b94b4eeb7cc170193}, journal = {J. Syst. Archit.}, keywords = {dblp}, pages = 102364, timestamp = {2024-04-09T07:10:49.000+0200}, title = {Process variation aware DRAM-Cache resizing.}, url = {http://dblp.uni-trier.de/db/journals/jsa/jsa123.html#AgarwallaDS22}, volume = 123, year = 2022 }