%0 Conference Paper %1 conf/vlsid/PandeyC03 %A Pandey, Rohit %A Chattopadhyay, Santanu %B VLSI Design %D 2003 %I IEEE Computer Society %K dblp %P 79-84 %T Low Power Technology Mapping for LUT based FPGA Ä Genetic Algorithm Approach". %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2003.html#PandeyC03 %@ 0-7695-1868-0

@inproceedings{conf/vlsid/PandeyC03, added-at = {2023-03-24T00:00:00.000+0100}, author = {Pandey, Rohit and Chattopadhyay, Santanu}, biburl = {https://www.bibsonomy.org/bibtex/26b06ef69ff725d11a75703c459f4850e/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2003}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183118}, interhash = {546ef7df43f1cf3e83023d1d81727bc9}, intrahash = {6b06ef69ff725d11a75703c459f4850e}, isbn = {0-7695-1868-0}, keywords = {dblp}, pages = {79-84}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:18:49.000+0200}, title = {Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach".}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2003.html#PandeyC03}, year = 2003 }