%0 Journal Article %1 journals/tcad/BilavarnGPB06 %A Bilavarn, Sébastien %A Gogniat, Guy %A Philippe, Jean Luc %A Bossuet, Lilian %D 2006 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 10 %P 1950-1968 %T Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations. %U http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#BilavarnGPB06 %V 25

@article{journals/tcad/BilavarnGPB06, added-at = {2023-06-26T00:00:00.000+0200}, author = {Bilavarn, Sébastien and Gogniat, Guy and Philippe, Jean Luc and Bossuet, Lilian}, biburl = {https://www.bibsonomy.org/bibtex/2c9eae66aeb3ae4225bfd4d4aef0dd03b/dblp}, ee = {https://doi.org/10.1109/TCAD.2005.862742}, interhash = {58b9db751c5fdc1b874f2da3054ab4e7}, intrahash = {c9eae66aeb3ae4225bfd4d4aef0dd03b}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 10, pages = {1950-1968}, timestamp = {2024-04-08T19:45:30.000+0200}, title = {Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#BilavarnGPB06}, volume = 25, year = 2006 }