%0 Conference Paper %1 conf/vlsid/VarmaPB13 %A Varma, B. Sharat Chandra %A Paul, Kolin %A Balakrishnan, M. %B VLSI Design %D 2013 %I IEEE Computer Society %K dblp %P 92-97 %T Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#VarmaPB13 %@ 978-1-4673-4639-9

@inproceedings{conf/vlsid/VarmaPB13, added-at = {2023-03-24T00:00:00.000+0100}, author = {Varma, B. Sharat Chandra and Paul, Kolin and Balakrishnan, M.}, biburl = {https://www.bibsonomy.org/bibtex/2abd2a469e1be95b2461425d271d41bdb/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2013}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSID.2013.169}, interhash = {59a4039031ffc0cb2d8fe24936afd740}, intrahash = {abd2a469e1be95b2461425d271d41bdb}, isbn = {978-1-4673-4639-9}, keywords = {dblp}, pages = {92-97}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:08:28.000+0200}, title = {Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2013.html#VarmaPB13}, year = 2013 }