%0 Conference Paper %1 conf/isicir/FujitaNITNA14 %A Fujita, Shinobu %A Noguchi, Hiroki %A Ikegami, Kazutaka %A Takeda, Susumu %A Nomura, Kumiko %A Abe, Keiko %B ISIC %D 2014 %I IEEE %K dblp %P 316-319 %T Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. %U http://dblp.uni-trier.de/db/conf/isicir/isic2014.html#FujitaNITNA14 %@ 978-1-4799-4833-8

@inproceedings{conf/isicir/FujitaNITNA14, added-at = {2017-04-24T00:00:00.000+0200}, author = {Fujita, Shinobu and Noguchi, Hiroki and Ikegami, Kazutaka and Takeda, Susumu and Nomura, Kumiko and Abe, Keiko}, biburl = {https://www.bibsonomy.org/bibtex/216c3c8e67e26debbe037a351abb8332e/dblp}, booktitle = {ISIC}, crossref = {conf/isicir/2014}, ee = {http://dx.doi.org/10.1109/ISICIR.2014.7029504}, interhash = {5d117016b2ae660a79a1582d68ebf6bd}, intrahash = {16c3c8e67e26debbe037a351abb8332e}, isbn = {978-1-4799-4833-8}, keywords = {dblp}, pages = {316-319}, publisher = {IEEE}, timestamp = {2017-04-25T12:42:02.000+0200}, title = {Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.}, url = {http://dblp.uni-trier.de/db/conf/isicir/isic2014.html#FujitaNITNA14}, year = 2014 }