%0 Journal Article %1 journals/tvlsi/ScottiBTP17 %A Scotti, Giuseppe %A Bellizia, Davide %A Trifiletti, Alessandro %A Palumbo, Gaetano %D 2017 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 12 %P 3509-3520 %T Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#ScottiBTP17 %V 25

@article{journals/tvlsi/ScottiBTP17, added-at = {2020-03-11T00:00:00.000+0100}, author = {Scotti, Giuseppe and Bellizia, Davide and Trifiletti, Alessandro and Palumbo, Gaetano}, biburl = {https://www.bibsonomy.org/bibtex/23a994022c30466dc9716199ae323dd23/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2750207}, interhash = {5d89ebef69f0ee97c5c408431f20fe18}, intrahash = {3a994022c30466dc9716199ae323dd23}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 12, pages = {3509-3520}, timestamp = {2020-03-12T11:42:01.000+0100}, title = {Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#ScottiBTP17}, volume = 25, year = 2017 }