%0 Journal Article %1 journals/jsa/Jeschke07 %A Jeschke, Hartwig %D 2007 %J J. Syst. Archit. %K dblp %N 10 %P 764-776 %T Chip size estimation for SOC design space exploration. %U http://dblp.uni-trier.de/db/journals/jsa/jsa53.html#Jeschke07 %V 53

@article{journals/jsa/Jeschke07, added-at = {2020-05-19T00:00:00.000+0200}, author = {Jeschke, Hartwig}, biburl = {https://www.bibsonomy.org/bibtex/2625771fffe825704d9ae685ac3efb637/dblp}, ee = {https://doi.org/10.1016/j.sysarc.2007.01.012}, interhash = {5dbb846e8ee9b1025b0cfc927bea6b3e}, intrahash = {625771fffe825704d9ae685ac3efb637}, journal = {J. Syst. Archit.}, keywords = {dblp}, number = 10, pages = {764-776}, timestamp = {2020-05-20T11:50:23.000+0200}, title = {Chip size estimation for SOC design space exploration.}, url = {http://dblp.uni-trier.de/db/journals/jsa/jsa53.html#Jeschke07}, volume = 53, year = 2007 }