%0 Conference Paper %1 conf/pdp/ValenteMPFFMFT16 %A Valente, Giacomo %A Muttillo, Vittoriano %A Pomante, Luigi %A Federici, Fabio %A Faccio, Marco %A Moro, Andrea %A Ferri, Serenella %A Tieri, Carlo %B PDP %D 2016 %I IEEE Computer Society %K dblp %P 373-376 %T A Flexible Profiling Sub-System for Reconfigurable Logic Architectures. %U http://dblp.uni-trier.de/db/conf/pdp/pdp2016.html#ValenteMPFFMFT16 %@ 978-1-4673-8776-7

@inproceedings{conf/pdp/ValenteMPFFMFT16, added-at = {2023-03-24T00:00:00.000+0100}, author = {Valente, Giacomo and Muttillo, Vittoriano and Pomante, Luigi and Federici, Fabio and Faccio, Marco and Moro, Andrea and Ferri, Serenella and Tieri, Carlo}, biburl = {https://www.bibsonomy.org/bibtex/2b979ac34d5796f7fb3c75e31dfbdf4b3/dblp}, booktitle = {PDP}, crossref = {conf/pdp/2016}, ee = {https://doi.ieeecomputersociety.org/10.1109/PDP.2016.86}, interhash = {6255b78be675010bb5f00b239a80fe13}, intrahash = {b979ac34d5796f7fb3c75e31dfbdf4b3}, isbn = {978-1-4673-8776-7}, keywords = {dblp}, pages = {373-376}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T15:08:23.000+0200}, title = {A Flexible Profiling Sub-System for Reconfigurable Logic Architectures.}, url = {http://dblp.uni-trier.de/db/conf/pdp/pdp2016.html#ValenteMPFFMFT16}, year = 2016 }