%0 Conference Paper %1 conf/eusipco/ChoiBP96 %A Choi, Seonil %A Bae, Jongwoo %A Prasanna, Viktor K. %B EUSIPCO %D 1996 %I IEEE %K dblp %P 1-4 %T Synthesis of memory-based VLSI architectures for discrete wavelet transforms. %U http://dblp.uni-trier.de/db/conf/eusipco/eusipco1996.html#ChoiBP96 %@ 978-888-6179-83-6

@inproceedings{conf/eusipco/ChoiBP96, added-at = {2021-08-09T00:00:00.000+0200}, author = {Choi, Seonil and Bae, Jongwoo and Prasanna, Viktor K.}, biburl = {https://www.bibsonomy.org/bibtex/297ebef09a3dfecd8d4f4350bb946758c/dblp}, booktitle = {EUSIPCO}, crossref = {conf/eusipco/1996}, ee = {https://ieeexplore.ieee.org/document/7082832/}, interhash = {632df88711a31bcbb084dcfdc37fcf1e}, intrahash = {97ebef09a3dfecd8d4f4350bb946758c}, isbn = {978-888-6179-83-6}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2024-04-10T21:37:16.000+0200}, title = {Synthesis of memory-based VLSI architectures for discrete wavelet transforms.}, url = {http://dblp.uni-trier.de/db/conf/eusipco/eusipco1996.html#ChoiBP96}, year = 1996 }